With semiconductor devices becoming lighter, thinner and smaller, necessary components of devices have been miniaturized significantly.
Conventionally, a wire bonding method is used for electrical connections between a semiconductor chip and a circuit board. Japanese Unexamined Patent Application Publication No. 11-121526 (published on Apr. 30, 1999) (Patent Document 1) discloses a technique, with which, to electrode pads formed on a miniaturized semiconductor chip, gold wires are wire-bonded at bonding positions shifted alternately, so as to have a wide gap between the gold wires. With this arrangement, a short-circuit between the gold wires can be prevented.
However, the wire bonding method requires a circuit board to have a region for wire bonding, outside of the region where the semiconductor chip is mounted. Therefore, a package size is not compact.
In order to reduce the area of the region for wire bonding, a flip-chip bonding method is proposed.
In the flip chip bonding method, bumps are formed on that surface (active element side) of a semiconductor chip on which active elements are to be provided. The active element side of the semiconductor chip and a circuit board are positioned to face each other, and the bumps and bonding pads formed on the circuit board are bonded together thereafter.
A C4 method and an ACF (anisotropic conductive film) method, with which an anisotropic conductive film is formed on a board for bonding, are typical flip-chip bonding methods.
FIGS. 8(a) and 8(b) are cross section views of a semiconductor device formed according to the C4 method.
In the C4 method, as FIG. 8(a) shows, a solder bump 510 is formed on an electrode pad 520, which is formed on a semiconductor chip 500. The semiconductor chip 500, on which the solder bump 510 is formed, and a circuit board 600 are positioned to face each other, and heated in a reflow furnace thereafter. The solder bump 510 is melted with the heat. As illustrated in the cross section view in FIG. 8(b), molten solder 550 bonds the semiconductor chip 500 and the circuit board 600 together.
Described below are the process of forming the solder bumps described above, for example. First of all, a wafer with a passivation film is sputtered with metal that will acts as a seed layer and a barrier metal layer in a plating process. Then, a plating mask is formed with photoresists. After that, electroplating with solder is carried out. Thereafter, the photoresists are removed and the seed metal is etched at the same time. Finally, the solder is melted with a reflow process, so as to make bumps.
FIGS. 9(a) and 9(b) are cross section views of a semiconductor device formed according to the ACF method.
As a cross section view FIG. 9(a) shows, in the ACF method, an ACF 640, where conductive particles 642 (such as resin balls coated with Au/Ni) are dispersed in a film-shaped binder resin 641, is attached to a circuit board 601. In addition, a bump 511 is formed on an electrode pad 520 of a semiconductor chip 501. As FIG. 9(b) shows, the semiconductor chip 501 and the circuit board 601 are pressure-bonded together with their active element side faced each other. At this time, the semiconductor chip 501 is pressured against the circuit board 601 under heat application with the ACF 640 between them. As a result, the conductive particles 642 are provided in between the bump 511 and the circuit board 601. With this arrangement, the conductive particles 642 connect the semiconductor chip 501 to the circuit board 601.
However, these methods have problems as follows.
For example, in the C4 method, the reflow process is needed for bonding a semiconductor chip to a circuit board. In the reflow process, it is difficult to use an organic circuit board because the semiconductor chip and the circuit board are heated.
In addition, it is also difficult to shorten (fine-pitch) the distance between the solder terminals, because the solder bumps should be formed. Moreover, a process for washing off flux is needed after bonding the semiconductor chip to the circuit board, because flux is used in the bonding process. As an unfortunate result, the whole process gets complicated.
The ACF method has a problem as well. In the ACF method, the semiconductor chip 501 and the circuit board 601 have electrical connections with the conductive particles 642, which are provided in between the bump 511 and the circuit board 601. The conductive particles 642 make the electrical connections by being in contact with the semiconductor chip 501 to the circuit board 601. Therefore, the semiconductor chip 501 to the circuit board 601 would easily have various contact resistances at different locations where they are connected with each other.
Consequently, the flip-chip bonding method adopting a local reflow method has been gaining attention in recent years.
FIGS. 10(a) and 10(b) are cross section views showing a semiconductor device formed according to the local reflow method.
As FIG. 10(a) shows, with the local reflow method, a gold (AU) wire bump 512 is formed on an electrode pad 520 of a semiconductor chip 502. In addition, solder pre-coat 650 is performed on a bonding pad 630 formed on a circuit board 602. As illustrated in FIG. 10(b), the semiconductor chip 502 and the circuit board 602 are heated and pressured. As a result, molten solder 651 solders the semiconductor chip 502 and the circuit board 602 together. Unlike the C4 method, the local reflow method makes it possible to solder without using flux.
FIGS. 11(a) and 11(b) are plan views showing a part of a circuit board, which is used in the flip-chip bonding method adopting the local reflow method. The plan views relate to, in particular, an embodiment of a portion of a bonding pad formed on a circuit board.
In FIG. 11(a), a conductor pattern 720, which constitutes a circuit, is formed on a circuit board 700. A bonding pad 730 is connected to the corresponding conductor patterns 720, and also positioned at such a position that the bonding pad 730 will be connected with a corresponding electrode pad formed on a semiconductor chip. In a region in which the bonding pads 730 is not formed, for example in a region on the conductor patterns 720, a solder resist 740 is provided, which is an insulation film.
For the solder pre-coating of the bonding pad 730, there are known methods according to the local reflow method, such as a Super Jufit method, a Super Solder method, a Screen Printing method and the like.
For example, Japanese Unexamined Patent Application Publication No. 7-74459 (published on Mar. 17, 1995) (Patent Document 2) discloses the Super Jufit method. In the Super Jufit method, the surface of a copper (Cu) pattern, which is formed on the circuit board 700, is treated with a special chemical for making the surface adhesive. Then, solder powder is adhered to the surface. After being coated with flux, the solder is reflowed, thereby being hot-leveled. With these steps, it is possible to carry out solder pre-coating on a copper pattern formed on the bonding pad 730.
Meanwhile, semiconductor chips have been more fine-pitched recently to pitches of less than 50 μm. Accordingly, the distance between the bonding pads 730 is needed to be more fine-pitched as well.
With the distance 731 between the bonding pads 730 fine-pitched, each solder pre-coat on the circuit board 700 can not take a wide region. As a result, in a process of providing a semiconductor chip on the circuit board 700, pre-coated solder could spill from the bonding pads 730, thereby resulting in a short-circuit between the adjacent bonding pads 730 with the spilled solder.
In order to prevent the short-circuit between the bonding pads 730 with the spilled solder, the solder for pre-coating should be reduced in amount. However, the decrease in the amount of the solder for pre-coating reduces an amount of solder contributing to the connection of the bonding pad 730 with a gold wire bump, formed on an electrode pad of a semiconductor chip, thereby resulting in a problem of unstable connections between the gold wire bump and the bonding pad 730.
In order to prevent the decrease of the solder contributing to the connection, another method is proposed. In the method, making bonding pads long can prevent the decrease of the solder contributing to the connection. In this method, the shape of bonding pads is quite long and thin because the width of a bonding pad depends on the distance between the bonding pads.
However, with bonding pads fine-pitched and being long and thin, as FIG. 11(b) shows, molten solder gathers at random positions because of surface tension caused in soldering the semiconductor chip and the bonding pads together. As a result, a solder bump 752 is formed in solder pre-coat 751.
These solder bumps 752 are formed at random positions on the long and thin bonding pads 730. Therefore, a possibility of bonding gold wire bumps of a semiconductor chip and molten solder together successfully decreases, thereby causing bad connections.
Japanese Unexamined Patent Application Publication No. 2000-77471 (published on Mar. 14, 2000) (Patent Document 3) discloses a technique in which a portion of a bonding pad 830 is formed wide, as illustrated in FIG. 12(a). With the technique, molten solder gathers on the widen portion 831 of the bonding pad 830. According to Japanese Unexamined Patent Application Publication No. 2005-11902 (published on Jan. 13, 2005) (Patent Document 4), as FIG. 12(b) shows, a widen portion 832 is made by protruding one of the long sides of a bonding pad 830.
In the arts described in these patent documents, the widen portion 831, as FIG. 12(a) shows, (or the widen portion 832, as FIG. 12(b) shows), is formed in such a manner that the widen portion 831 (or the widen portion 832) will face a gold wire bump of a semiconductor chip when the solder-bonding is carried out. As FIG. 12(c) shows, molten solder 851 tends to gather on the widen portion 831, so as to make it possible to increase the amount of the solder contributing to the solder bonding.
In addition, Japanese Unexamined Patent Application Publication No. 9-293957 (published on Nov. 11, 1997) (Patent Document 5) discloses a method, in which pads for storing solder are formed with lead wires from electrode pads. In the method, solder from the pads is used for soldering electrode pads.
However, with the conventional arrangements described above, it is difficult to make a circuit board, with which it is possible to narrow the connection distance between the electrodes of a semiconductor device, and also to have a sufficient thickness of the solder pre-coat for the soldering process at the same time.
For example, the bonding pads disclosed in Patent Document 3 or Patent Document 4, have such a shape that the narrower connection distance between the electrodes of the semiconductor device results in the reduction of the distance between adjacent bonding pads. This phenomenon occurs significantly in case where a further wider portion of a bonding pad is formed so that more solder is used to bond the connection pad to a gold wire bump of a semiconductor.
As FIG. 12(d) shows, with the reduction of the distance between bonding pads, the pre-coated solder would be spilled from a bonding pad 830, thereby causing a short-circuit between the adjacent bonding pads 830.
In order to prevent the short-circuit with spilled solder, there could be an arrangement in which, as illustrated in FIG. 13(a), a bonding pad 930 is formed narrower, so as to make it possible to widen the distance 931 between the adjacent bonding pads 930. In this case, however, as FIG. 13(b) shows, molten solder 951 melted at a widen portion 932 is reduced in amount. As a result, the solder contributing to the connection between a gold wire bump and the bonding pad 930 is reduced in amount. In short, connection defects would occur because the amount of solder for connecting a gold wire bump to a bonding pad is not sufficient.